FIG. 1 shows an example memory cell 100 which is a SRAM (static random access memory) cell. The present invention is described for SRAM cells, but the present invention may be practiced with other types of memory cells as would be apparent to one of ordinary skill in the art from the description herein. A SRAM is comprised of an array of such a SRAM cell 100. For some applications, data of the SRAM is simultaneously shared by a plurality of memory accessing devices. For such applications, the SRAM cell of the SRAM array is a multiport SRAM cell for providing access to the data of the SRAM cell for a plurality of memory accessing devices.
The SRAM cell 100 of FIG. 1 includes a bistable loop of a first inverter 102 and a second inverter 104. The first inverter 102 is comprised of a first PMOSFET (P-channel metal oxide semiconductor field effect transistor) 106 and a first NMOSFET (N-channel metal oxide semiconductor field effect transistor) 108 coupled between a positive power supply VCC 118 and the ground node 120. The second inverter 104 is comprised of a second PMOSFET 110 and a second NMOSFET 112 coupled between the positive power supply VCC 118 and the ground node 120. The input of the first inverter 102 is coupled to the output of the second inverter 104 at a first bistable node 114, and the input of the second inverter 104 is coupled to the output of the first inverter 102 at a second bistable node 116. The first and second bistable nodes 114 and 116 store the data of the SRAM cell 100, as known to one of ordinary skill in the art of electronics.
In addition, the example SRAM cell 100 includes a first pass gate 122 comprising a first port of the SRAM cell 100 and a second pass gate 124 comprising a second port of the SRAM cell 100. The first and second pass gates 122 and 124 are comprised of a pair of a PMOSFET and an NMOSFET, and such implementation of pass gates is known to one of ordinary skill in the art of electronics.
First access control signals R/WA1 and R/WA1* (the complement of R/WA1) are provided by a first memory accessing device to the first pass gate 122 for accessing the SRAM cell 100 for either reading data from or writing data to the SRAM cell 100. Second access control signals R/WA2 and R/WA2* (the complement of R/WA2) are provided by a second memory accessing device to the second pass gate 124 for either reading data from or writing data to the SRAM cell 100.
Referring to FIG. 2, in the prior art, the first memory accessing device accesses the SRAM cell 100 for a first read or write operation 136 via the first pass gate 122 comprising the first port of the SRAM cell 100 during a first cycle 132 of a clock signal 130. Then, the second memory accessing device accesses the SRAM cell 100 for a second read or write operation 138 via the second pass gate 124 comprising the second port of the SRAM cell 100 during a second cycle 134 of the clock signal 130. Such operations are performed during separate clock cycles 132 and 134 for prevention of contention between such operations 136 and 138. For example, referring to FIG. 3, if both the first and second read or write operations 136138 by the first and second memory accessing devices were performed during the same first cycle 132 of the clock signal 130, then such write and read operations 136 and 138 may overlap resulting in contention between the first and second memory accessing devices.
Thus, to prevent such contention in the prior art, each read or write operation is performed within a respective separate cycle of the clock signal. However, performance of each read or write operation within a respective separate cycle of the clock signal limits the bandwidth of such operations to the frequency of the clock signal.
Thus, a mechanism is desired for synchronizing a read operation and a write operation within one cycle of a clock signal for increasing the bandwidth of such operations while at the same time preventing contention between such operations.